In recent years, liquid crystal displays (LCD), characterized by their thinness, light-weightiness, and low power consumption, have been widely spread, and used for displays of mobile devices such as mobile phones, cellular phones, PDAs (personal digital assistants), and notebook computers. However, as technologies to enlarge screens of liquid crystal displays and support moving pictures advance, liquid crystal displays are used for not only mobile devices, but also stationary large-screen display devices and large-screen LCD televisions. As such liquid crystal display devices, active matrix LCD devices allowing high definition display are currently in use. First, referring to FIG. 17, a typical configuration of an active matrix LCD device will be described. Note that a main structure connected to a pixel of the liquid crystal display unit is schematically shown by an equivalent circuit diagram in FIG. 17.
The display unit 960 of the active matrix LCD device has generally a structure comprising a semiconductor substrate on which transparent pixel electrodes 964 and thin film transistors (TFT) 963 are disposed in matrix (for instance 1280×3 pixel columns×1024 pixel rows in the case of a color SXGA panel), a counter-substrate having a transparent electrode 966 on the entire surface, and a liquid crystal sealed between the two substrates.
The TFTs 963, having a switching function, are on/off controlled by a scanning signal, such that, when the TFTs 963 are turned on, a grayscale voltage corresponding to a picture data signal is applied to the pixel electrodes 964 and the transmittance of the liquid crystal is changed by the potential difference between each pixel electrode 964 and the electrode 966 of the counter-substrate. Even after the TFTs 963 are turned off, a picture is displayed by having a liquid crystal capacitor 965 maintain this potential difference for a predetermined time.
On the semiconductor substrate, a lattice-like interconnection (wiring) of data lines 962 for sending a plurality of level voltages (grayscale voltages) applied to each pixel electrode 964 and scanning lines 961 for sending the scanning signals are formed (in the case of the aforementioned color SXGA panel, 1280×3 data lines and 1024 scanning lines). The scanning lines 961 and the data lines 962 provide a large capacitive load due to the capacitance generated at the intersections with each other and the capacitance of the liquid crystal interposed between the electrode of the counter-substrate and these lines.
Meanwhile, the scanning signals are supplied from a gate driver 970 to scanning lines 961, and the grayscale voltages are supplied to respective pixel electrodes 964 by a data driver 980 via the data lines 962. Further, the gate driver 970 and the data driver 980 are controlled by a display controller 950. A clock CLK, control signals, and power supply voltages needed are supplied by the display controller 950, and image data is supplied to the data driver 980. Currently, the image data is mainly digital data.
Data for one frame is rewritten every frame period ( 1/60 second) and is selected successively per scanning line from one row of pixels to the next (every line). The grayscale voltages are supplied from respective data lines during the selection period.
Further, whereas it is sufficient for the gate driver 970 to supply at least two-valued scanning signals, the data driver 980 is required to drive the data lines with grayscale voltages of multi-valued levels corresponding to the number of grayscale levels. Therefore, the data driver 980 comprises a decoder that converts the image data into grayscale voltages and a digital-to-analog converter circuit (DAC) composed of an operational amplifier that amplifies the grayscale voltages and outputs them to the data lines 962.
Further, the recent trend in the liquid crystal display devices is to demand higher picture quality (with an increasing number of colors), and at least 260,000 colors (6-bit image data for each of RGB), or sometimes equal to or more than 26,800,000 colors (8-bit image data for each of RGB) are demanded.
Accordingly, in the data driver that outputs the grayscale voltage corresponding to multi-bit image data, the circuit scale of the DAC increases, and as a result, so do the chip area of the data driver LSI and costs. Therefore an operational amplifier and a digital-to-analog converter (DAC) that allow the area of the data driver to be reduced are in demand.
FIG. 18 is a circuit diagram showing the configuration of a differential amplifier used in a buffer circuit (a drive circuit that drives the data lines) in the data driver 980 shown in FIG. 17 (for analogous information, for instance, refer to Patent Document 1). This differential amplifier is an offset canceling amplifier that cancels an output offset caused by element variations, and its purpose is different from that of the present invention, however, it will be described for the sake of comparison.
Referring to FIG. 18, this conventional differential amplifier comprises a pair of NMOS transistors M3 and M4 forming a first differential pair and having commonly-connected sources connected to a low potential side power supply VSS via a constant current source M8, a pair of NMOS transistors MS and M6 forming a second differential pair and having commonly-connected sources connected to the low potential side power supply VSS via a constant current source M9, a PMOS transistor M2 having the source connected to a high potential side power supply VDD, the gate and the drain connected to each other, and the drain commonly connected to the drains of the NMOS transistors M4 and M6, a PMOS transistor M1 having the source connected to the high potential side power supply VDD, the gate connected to the gate of the PMOS transistor M2, and the drain commonly connected to the drains of the NMOS transistors M3 and M5, a PMOS transistor M7 having the source connected to the high potential side power supply VDD, the gate connected to the drain of the PMOS transistor M1, and the drain connected to an output terminal Vout, and forming an amplifier stage, a constant current source M10 connected between the output terminal Vout and the low potential side power supply VSS, capacitors C11 and C12 connected across the gate of the transistor M4 and the low potential side power supply VSS and the gate of the transistor M3 and the low potential side power supply VSS, respectively, switches SW11 and SW12 connected between the gate of the NMOS transistor M6 and an input terminal Vin and between the gate of the NMOS transistor M6 and the output terminal Vout, respectively, a switch SW16 connected between the gate of the NMOS transistor M3 and the input terminal Vin, and a switch SW13 connected between the gate of the NMOS transistor M4 and the output terminal Vout. The gate of the NMOS transistor M5 is connected to the input terminal Vin.
FIG. 19 is a timing chart showing the switch control of the circuit shown in FIG. 18. Referring to FIG. 19, in the circuit shown in FIG. 18, the switches SW11, SW13, and SW16 are turned on during a period t1, which is one data output period, and the switch 12 is turned off. The input pair of the differential pair (M3 and M4) receives an input voltage Vin and an output voltage Vout (fedback), and the input pair of the differential pair (M5 and M6) receives the input voltage Vin. At this time, a voltage (Vin+Vf) containing an offset voltage is stored in the capacitive element C11, and the input voltage Vin is stored in the capacitive element C12.
In a period t2 after this, the switches SW11, SW13, and SW16 are in an off state and the switch SW12 is in an on state. The input pair of the differential pair (M3 and M4) respectively receives the voltages Vin and (Vin+Vf) stored in the capacitive elements C12 and C11, and the input pair of the differential pair (M5 and M6) respectively receives the input voltage Vin and the output voltage Vout. Since the gate voltages of the transistors M3, M4, and M5 do not change during the periods t1 and t2, the gate voltage of the transistor M6 is maintained as well. In other words, Vout=Vin, therefore the circuit shown in FIG. 18 is able to cancel the output offset, and amplify and output a voltage equal to the input voltage.
[Patent Document 1] Japanese Patent Kokai Publication No. JP-P2001-292041A
The disclosure of the above document is incorporated herein by reference thereto.